Prof. Seong-Ook Jung’s self-timed pulsed latch technique was accepted in IEEE Journal of Solid-State Circuits (JSSC), the most renowned journal in circuit and system field.

The proposed latch reduces the hold time by 77% and minimum VDD by 300 mV for stable operation in low VDD region, which can further accelerates the VDD scaling.

This research was made by doctor Hanwool Jeong and professor Seong-Ook Jung of VLSI system laboratory.