Prof. Jung's paper, “A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface”, has been published in IEEE Journal of Solid-State Circuits (JSSC), one of the most highly-ranked journals in circuit design field (Impact Factor 4.6).

The proposed TSV I/O effectively mitigates signal integrity degradation occurring in low-voltage & high-speed operation by utilizing a hybrid equalizer, direct feedback 1-tap DFE, and quadrature clock error corrector.

This work was led by Taeryeong Kim (Ph.D. Candidate) and Prof. Seong-Ook Jung of the VLSI system laboratory.