< BK21 플러스 BEST 정보기술 사업단 세미나 개최 안내 >

개최일시 : 2016년 10월 25일 화요일 17:00 ~ 18:00

개최장소 : 제 3공학관 C616호

세미나 제목 : Design Methodologies for Low Power Computing with 3D Multi-core Processors

발표초록 :                                                                                                                             

As we reach the mobile era, power reduction is a keyword that integrated circuit (IC) industry considers as top priority. Not only for mobile devices that require long battery life and energy efficiency, but also for data centers that wish to increase their GHz/Watt performance requires to tackle this power reduction issue and have it set as their top priority goal. In this effort, three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs) have gained a great deal of attention as a viable solution for low-power IC designs. In this perspective, this talk discusses how low-power ICs can be designed using the promising 3D IC technology. In detail, this talk discusses how 3D IC design methodologies can be setup, what key design techniques are needed for more power reduction, and how maximum power reduction can be achieved using a commercial-grade multi-core CPU (OpenSPARC T2).  Using all design techniques that this talk cover, a 3D multi-core CPU can achieve -36% power reduction in Core level and -27% in full-chip level.

강연자 : Dr. Taigon Song / Synopsys Inc.

초청자 : 전기전자공학과 교수 노원우