- 세미나 [11/25] A design of 12-bit 125-MS/s 2.5-bit/Cycle SAR-based pipeline ADC employing a loop-based gain-boosting amplif
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< BK21 플러스 BEST 정보기술 사업단 세미나 개최 안내 >
개최일시 : 2019년 11월 25일 (월) 16:00 ~ 17:00
개최장소 : 제 3공학관 C616호
세미나 제목 : A design of 12-bit 125-MS/s 2.5-bit/Cycle SAR-based pipeline ADC employing a loop-based gain-boosting amplifier
The demand for cutting-edge CMOS technology has grown explosively with an appearance of mobile computing and artificial intelligence. Unfortunately, since the narrow channel length in the advanced CMOS technology has continued to reduce intrinsic gain of a transistor, a multi-stage amplifier design has been popular and mandatory to achieve a required gain. With the demand of a multi-stage amplifier, the compensation technique has been popular to overcome phase margin issue. Since the pole-splitting concept by a miller capacitor was introduced in the 1980’s, a lot of advanced miller compensation techniques and design guideline have been published so far. Another technique of using pole-zero doublet in a multi-stage amplifier design has been introduced as well. A main idea of this technique is to use feed-forward path for creating a left-hand plain zero, then place it exactly on the 2nd pole location. By doing this, it creates a pole-zero doublet and therefore, a disadvantage of the 2nd pole effect in terms of the phase will be canceled out by the left-hand zero.
This seminar covers a different approach of loop-based gain-boosting technique to provide a better matching of pole-zero doublet and a smaller power consumption, while achieving DC gain as high as multi-stage amplifiers. As an example of how to use this amplifier, pipeline ADCs are chosen because it requires a residue amplifier between the stages. A proposed ADC architecture combines a multi-bit per cycle SAR ADC and a pipeline approach to achieve a high-speed performance. Also, a 2.5 bit/cycle SAR ADC is applied as a sub-ADC in pipeline stages, and a resistor-DAC is utilized for SAR and residue operation. As a result, the prototype ADC achieves 12-bit and 125-MS/s with a loop-based gain-boosting amplifier.
강연자 성함&직함 / 소속 : Chulhyun Park / Apple Inc., Cupertino, CA / Texas A&M University, College Station, TX
초청자 : 전기전자공학과 교수 윤일구