| 2024-04 |
A New Fail Address Memory Architecture for Cost-Effective ATE |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2024-04 |
Reconfigurable Multi-bit Scan Flip-Flop for Cell-Aware Diagnosis |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2023-09 |
STRAIT: Self-Test and Self-Recovery for AI Accelerator |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2023-08 |
Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2023-07 |
TRUST: Through-Silicon via Repair Using Switch Matrix Topology |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2023-04 |
Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2023-04 |
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
|
| 2023-01 |
Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2022-12 |
A Hybrid Test Scheme for Automotive IC in Multi-site Testing |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2022-11 |
Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis |
IEEE Transactions on Circuits and Systems II: Express Briefs
|
| 2022-11 |
SPAR: A New Test Point Insertion Using Shared Points for Area Overhead Reduction |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
|
| 2022-08 |
Multibank Optimized Redundancy Analysis Using Efficient Fault Collection |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2022-06 |
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2022-04 |
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2022-03 |
Reduced-Pin-Count BOST for Test-Cost Reduction |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2021-10 |
ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory |
IEEE Access
|
| 2021-09 |
Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks |
SENSORS
|
| 2021-09 |
Reconfigurable Scan Architecture for High Diagnostic Resolution |
IEEE Access
|
| 2021-08 |
A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive Ics |
IEEE Access
|
| 2021-07 |
A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key |
IEEE Access
|
| 2021-06 |
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2021-05 |
Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory |
IEEE Access
|
| 2021-04 |
On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug |
IEEE Access
|
| 2021-02 |
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process |
IEEE Access
|
| 2020-12 |
A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction |
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
|
| 2020-11 |
Prediction-Based Error Correction for GPU Reliability with Low Overhead |
ELECTRONICS
|
| 2020-10 |
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2020-09 |
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2020-09 |
Fine-Grained Defect Diagnosis for CMOL FPGA Circuits |
IEEE Access
|
| 2020-09 |
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks |
SENSORS
|
| 2020-08 |
Advanced Low Pin Count Test Architecture for Efficient Multi Site Testing |
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
|
| 2020-03 |
GPU-Based Redundancy Analysis Using Concurrent Evaluation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2020-02 |
Ecient Systolic-Array Redundancy Architecture for Oine/Online Repair |
ELECTRONICS
|
| 2019-10 |
Dynamic Built-In Redundancy Analysis for Memory Repair |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-08 |
A low-cost concurrent TSV test architecture with lossless test output compression scheme |
PLOS ONE
|
| 2019-08 |
Test-Friendly Data-Selectable Self-Gating (DSSG) |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2019-03 |
Highly Reliable Redundant TSV Architecture for Clustered Faults |
IEEE TRANSACTIONS ON RELIABILITY
|
| 2019-03 |
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2019-01 |
TSV Repair Architecture for Clustered Faults |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2018-12 |
Test resource reused debug scheme to reduce the post-silicon debug cost |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2018-09 |
A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test |
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
|
| 2018-09 |
A debug scheme to improve the error identification in post-silicon validation |
PLOS ONE
|
| 2018-07 |
Fault Group Pattern Matching with Efficient Early Termination for High-Speed Redundancy Analysis |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2018-04 |
Thermal Aware Test Scheduling for NTV Circuit |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2018-03 |
Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation |
IEEE TRANSACTIONS ON RELIABILITY
|
| 2018-01 |
An Area-Efficient BIRA With 1-D Spare Segments |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2017-12 |
A novel X-filling method for capture power reduction |
IEICE ELECTRONICS EXPRESS
|
| 2017-10 |
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2017-09 |
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2017-07 |
DVFS-aware refresh management for 3D DRAM over processor architecture |
ELECTRONICS LETTERS
|
| 2017-07 |
Reconfigurable scan architecture for test power and data volume reduction |
IEICE ELECTRONICS EXPRESS
|
| 2017-06 |
R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies |
IEEE TRANSACTIONS ON RELIABILITY
|
| 2017-06 |
Proof of Concept of Home IoT Connected Vehicles |
SENSORS
|
| 2017-03 |
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2017-03 |
Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2017-02 |
Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2017-02 |
A low-cost DAC BIST structure using a resistor loop |
PLOS ONE
|
| 2017-02 |
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2017-01 |
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time |
IEEE TRANSACTIONS ON COMPUTERS
|
| 2016-10 |
A New 3-D Fuse Architecture to Improve Yield of 3-D Memories |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2016-10 |
A Survey of Repair Analysis Methods for Memories |
ACM COMPUTING SURVEYS
|
| 2016-07 |
Parallelized Network on Chip-reused Test Access Mechanism for Multiple Identical Cores |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2016-06 |
Optimized Built-in Self Repair for Multiple Memories |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2016-02 |
Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2015-09 |
Lifetime reliability enhancement of microprocessors: Mitigating the impact of negative bias temperature instability |
ACM COMPUTING SURVEYS
|
| 2015-09 |
3-D Stacked DRAM Refresh Management with Guaranteed Data Reliability |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2015-08 |
A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect |
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
|
| 2015-08 |
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2015-08 |
Fully Programmable Memory BIST for Commodity DRAMs |
ETRI JOURNAL
|
| 2015-06 |
Histogram-Based Calibration Method for Pipeline ADCs |
PLOS ONE
|
| 2015-06 |
Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency |
SENSORS
|
| 2015-06 |
Reduced-code test method using sub-histograms for pipelined ADCs |
IEICE ELECTRONICS EXPRESS
|
| 2015-06 |
Multi-operation-based Constrained Random Verification for On-Chip Memory |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2015-06 |
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories |
IEEE TRANSACTIONS ON RELIABILITY
|
| 2015-03 |
A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability |
IEEE TRANSACTIONS ON RELIABILITY
|
| 2015-02 |
New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors |
ETRI JOURNAL
|
| 2014-11 |
A delay test architecture for TSV with resistive open defects in 3-D stacked memories |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-11 |
A BIRA for memories with an optimal repair rate using spare memories for area reduction |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-05 |
Recovery-enhancing task scheduling for multicore processors under NBTI impact |
IEICE ELECTRONICS EXPRESS
|
| 2014-05 |
A new fuse architecture and a new post-share redundancy scheme for yield enhancement in 3-D-stacked memories |
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
|
| 2014-04 |
Interleaving test algorithm for subthreshold leakage-current defects in DRAM considering the equal bit line stress |
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
|
| 2014-04 |
A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture |
ETRI JOURNAL
|
| 2014-03 |
A novel test access mechanism for parallel testing of multi-core system |
IEICE ELECTRONICS EXPRESS
|
| 2013-12 |
Dynamic thermal management for 3D multicore processors under process variations |
IEICE ELECTRONICS EXPRESS
|
| 2013-10 |
A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory |
ETRI JOURNAL
|
| 2013-07 |
Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations |
IEICE ELECTRONICS EXPRESS
|
| 2013-06 |
Efficient Multi-site Testing Using ATE Channel Sharing |
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
|
| 2013-06 |
A very efficient redundancy analysis method using fault grouping |
ETRI JOURNAL
|
| 2013-02 |
Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter |
IEICE TRANSACTIONS ON COMMUNICATIONS
|
| 2013-02 |
Built-In Self-Test for Static ADC Testing with a Triangle-Wave |
IEICE TRANSACTIONS ON ELECTRONICS
|
| 2013-02 |
IEEE 1500 표준 기반의 효율적인 프로그램 가능한 메모리 BIST |
전자공학회논문지
|
| 2013-02 |
Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices |
ETRI JOURNAL
|
| 2013-02 |
Simultaneous Static Testing of A/D and D/A Converters Using a Built-in Structure |
ETRI JOURNAL
|
| 2012-10 |
An accurate diagnosis of transition fault clusters based on single fault simulation |
IEICE ELECTRONICS EXPRESS
|