< BK21+ BEST Seminar Series Announcement> 

Time and Date : 14:30 ~ 15:30 Thursday 12/26/2019

Place : C616, Engineering Building #3

Title : Digital IC Layout Design Automation for Advanced Technology Nodes - Global Placement, Routability Analysis, and 3-D IC Floorplan Representation
Abstract:
While "Moore's Law" and "Dennard Scaling" have shown the correction of slowing-down, industry-leading foundries are relentlessly continuing to develop sub-5nm technologies.  IC industry requires even more sophisticated design methodologies to overcome nontrivial/complicated challenges.  IC layout design directly impacts on timing closure, die utilization, routability, and design turnaround time (TAT); these in turn affect the classic design metrics of operating frequency, yield, power consumption and cost.  In this talk, Dr. Kang briefly describes the fundamental physical design flow, then presents new IC design automation techniques in the highlight of (1) the state-of-the-art global placement algorithm, (2) SAT- (satisfiability-) based design rule-correct routability analysis and diagnosis, and (3) 3-D IC floorplan representation method.

Presenter: Ilkwon Kang, Software Engineer / Cadence Design Systems

Host: Prof. Kang, Sungho, Yonsei EEE