< BK21 플러스 BEST 정보기술 사업단 세미나 개최 안내 > 

개최일시 : 2019년 12월 26일 (목) 14:30 ~ 15:30

개최장소 : 제3공학관 C616호

세미나 제목 : Digital IC Layout Design Automation for Advanced Technology Nodes - Global Placement, Routability Analysis, and 3-D IC Floorplan Representation

내용 :

While "Moore's Law" and "Dennard Scaling" have shown the correction of slowing-down, industry-leading foundries are relentlessly continuing to develop sub-5nm technologies. IC industry requires even more sophisticated design methodologies to overcome nontrivial/complicated challenges. IC layout design directly impacts on timing closure, die utilization, routability, and design turnaround time (TAT); these in turn affect the classic design metrics of operating frequency, yield, power consumption and cost. In this talk, Dr. Kang briefly describes the fundamental physical design flow, then presents new IC design automation techniques in the highlight of (1) the state-of-the-art global placement algorithm, (2) SAT- (satisfiability-) based design rule-correct routability analysis and diagnosis, and (3) 3-D IC floorplan representation method.

강연자 성함&직함 / 소속 : 강일권 Software Engineer / Cadence Design Systems 

초청자 : 전기전자공학과 교수 강성호