< BK21 플러스 BEST 정보기술 사업단 세미나 개최 안내 >
-개최일시 : 2017년 08월 28일 월요일 15:00 ~ 16:00
-개최장소 : 제 2공학관 B037호
-세미나 제목 :
Nanoscale Surface Engineering for Advanced Nanoelectronics: Thin Film Process
& Engineering in Nanofabrication
-발표초록 : Surface
engineering is a sub-discipline of materials science and engineering that deals
with the surface of solid matter. Historically, the surface engineering
involves altering properties of the solid-state surface, which interacts with
surrounding environment, in order to reduce the surface degradation over time.
Conventionally, from tribological point of view, the surface engineering has
received a great deal of attention, especially for
wear/friction/corrosion/fatigue-protection coating technologies in automotive
and aerospace industries, pursuing improved hardness and thermal stability with
sufficiently good adhesion.
Meanwhile, we are already living in a nano-era (i.e. length scale
of approximately 1 - 100 nanometer range) that requires nanoscale surface
engineering. In the modern nanotechnologies, accordingly, the advanced
nano-surface engineering basically aims to provide additional functionality,
such as mechanical, electrical, magnetic, and optical characteristics, to the
solid surface, not found naturally in the original solid surface. It can be
enabled through surface modification/functionalization, where a material surface
itself can be transformed or through surface coating technologies, where
additional structures and compositions can be added.
In this seminar, therefore, we focus on recent trends in the
advanced nanoscale surface engineering implemented for modern nanoelectronics.
As Si-based technology node nears ~10 nm and approaches its physical limit,
alternative surface engineering techniques based on atomic layer deposition
(ALD) and atomic layer etching (ALE), are extremely required for further
extension of Moore’s law,
together with structural challenges of integration-feasible 3D nanostructures
such as 3D FinFETs and nanowires (NWs) in place of the conventional planar
MOSFET. In addition, extremely fine-feature patterning is also required to
satisfy the increasing process complexity of modern electronic devices beyond
the sub-10 nm technology regime. Therefore, we further explore nanoscale
bottom-up hybrid nanofabrication methods, based on various self-assembled
nanopatterning processes using nanotemplates and area-selective ALD.
-강연자 : 김우희 박사/Micron
-초청자 : 전기전자공학과